1. Field of the Invention
The present invention relates to statistical estimation of leakage current in a semiconductor integrated circuit.
2. Description of the Related Art
Recently, with the higher integration of semiconductor integrated circuits, leakage current therein tends to increase. Leakage current is current that flows in an electronic circuit through a portion that should not have any current flow. Leakage current increases power consumption and the heat generated by the semiconductor integrated circuit, and can cause degraded circuit performance.
Therefore, it is important to correctly estimate leakage current and to take countermeasures when a circuit is designed. Meanwhile, due to reductions in chip dimension, variation of leakage current caused by the reductions has increased. Thus, conventional statistical analysis tends to pessimistically estimate the maximal current leak of a circuit. Therefore, a technique of more accurately estimating current leak is demanded.
Generally, it is known that element variation and wiring variation handled by statistical analysis has an intra-chip variation component that is independent for each element and wiring, and an inter-chip variation component that is correlated among elements/wiring. Conventionally, an approach of statistically estimating leakage current includes a Monte Carlo method of repeating for several tens of thousands of times a deterministic leakage current analysis of several million elements, and an approach of performing the multiple (numerical) integral of several million variables using the probability distribution of each element.
Other approaches include an approach of statistically estimating leakage current taking into account only the intra-chip variation component and an approach of statistically estimating leakage current by fixing a leak distribution function of the inter-chip variation component as a normal function or a logarithmic normal function such as that described in, for example, Japanese Patent Application Laid-Open Publication No. 2003-316849, and by Rajeev Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester in “Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 12, No. 2, February 2004, pp. 131-139.
However, although both the Monte Carlo method and the approach of statistically estimating a leakage current by multiple integral using the probability distribution of each element can correctly estimate the leakage current, a problem arises in that the calculations involved for both the Monte Carlo method and the approach, consume an enormous amount of time and the calculation is nearly impossible.
The conventional techniques disclosed in Japanese Patent Application Laid-Open Publication No. 2003-316849 and by Rajeev Rao, et al. can not accurately handle the inter-chip variation component and therefore, a problem arises in that the accuracy of the leakage current analysis is degraded. More specifically, when the correlation among elements/wiring due to the inter-chip distribution is strong, the shape of the leak distribution is not necessarily that of a normal distribution or a logarithmic normal distribution. Therefore, the error of the maximal leakage current value (for example, about 17%) increases and, as a result, correction of the circuit design after delivery occurs. Therefore, a problem has arisen in that the work load on designers increases and the time period for designing becomes longer.